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ZL10310/ZL10311 Digital Television DVB-T-On-a-Chip Processor
Data Sheet Features
* * * * * * * * * * * * * * * DTV-SoC for Digital Terrestrial Television (DTT) On-chip DVB-T COFDM demodulator with FEC. 6 Video DACs on-chip, for Composite or Component (RGB or Y U/V) Analog Video Twin PAL/NTSC DENCs Low Power (<1.4W Typical) Low Component Count Unified SDRAM controller I2S Digital Audio Input I2S and S/PDIF Digital Audio outputs MPEG-2 Audio & Video decoders PowerPC 405TM CPU Core with 16k/16k cache, Memory manager and Virtual memory system Complete Linux-based Software Development Kit (SDK) IDE interface Inputs for external MPEG-2 Transport Streams, allowing support for external demodulators (e.g. Cable TV, Satellite TV) Conditional Access (CA) DVB-descrambler
Issue 1.0 November 2002
Ordering Information ZL10310/GAC ZL10311/GAC 388 ball EPBGA 388 ball EPBGA
0 0C to +70 0C * * * * * * * Smart Card Interface Infrared & UART interface DVB-compatible Common Interface (CI) control and bitstream interfaces Multi-stream multiplexing to support internal and external demodulators External Modem support interface Supports MacrovisionTM Copy Protection (ZL10311 only; available to Macrovision license holders only) Dolby Digital* Decoding - (ZL10311 only; available to Dolby Digital* license holders only *awaiting certification)
Bitstream O/P /Second Bitstream I/P Smart Card Stereo Audio 2 I S DAC S/PDIF
ZL10310 / ZL10311 DTV-SOC
De-mod /JTAG
EXTIN JTAG
Audio Decoder
Bitstream Multiplexing & Control
Descrambler
System DeMultiplex
ADC IN /De-mod AGC B Flash IDE CI Control Smart Card CODEC/modem 2 IC UART/IRDA BIT I/O
ADCIN
COFDM DeModulator & FEC
Video Decoder
AUX Bus
Video Scaler / Blender
Cached PowerPC 405 Sub System
R
Comp
Peripherals
Video Video DENCs /DACs 8k Boot ROM SDRAM Controller SDRAM Controller
Y+U/V RGB
Analog Video
Power Management
SDRAM 1 BUS
SDRAM 0 BUS (optional)
Figure 1 - Block Diagram of ZL10310 and ZL10311
1
ZL10310/ZL10311
Applications
* * * * * * * * Low power, small footprint TV adaptors Integrated Digital Televisions (iDTV) Digital terrestrial set-top boxes DTT / DVD Combo DVB-T radio receivers Terrestrial / Satellite Combo Terrestrial / Cable Combo Terrestrial / IP (Internet Protocol) Combo
Data Sheet
Description
Zarlink Semiconductor has responded to market demand by integrating its key DVB-T compliant COFDM demodulation technology with Set Top Box functionality (MPEG-2 A/V decoder and system interfaces) together with a high performance CPU to offer a "DVB-T On-a-Chip" solution. The ZL10310 DVB-T On-a-Chip, can address a wide range of DVB-T consumer electronic products. At the entry level it can be used to build ultra-compact Free-To-View Digital TV adaptors (such as for FreeView in the UK), yet consumes less than 4W of power in full operational mode. This level of compactness also considerably eases the integration of DVB-T receiver technology inside integrated Digital TV sets (iDTV's) where space considerations and thermal management are key design issues. The ZL10310 is based upon an industry standard PowerPC 405TM RISC processor, which has Virtual and Memory Management sub-systems. This permits the device to be effectively deployed in compelling applications such as interactive Digital TV which are able to exploit the superior processing performance offered by the PowerPC processor core. The PowerPC provides an ideal platform for running robust open standard operating systems such as Linux which can benefit system developers in a number of key areas: * * * * * * Unified software development environment, from entry level basic channel zapper systems through to fully interactive high performance Digital Set Top Boxes. Re-use of software code from multiple projects Exploit software code developed in the Linux community. Low cost-per-seat software development environment. Familiar software development environment. Royalty free.
Also available is the ZL10311 DVB-T On-a-Chip, which additionally offers Dolby Digital1 multi-channel audio decoding, and MacrovisionTM Copy Protection for applications requiring Dolby Audio and Pay TV services.
1. The ZL10311 device is awaiting Dolby Certification
2
Zarlink Semiconductor Inc.
Data Sheet
ZL10310/ZL10311 Table of Contents
1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.0 Device Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.0 Typical Digital Television (DTV) Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.0 Functional Blocks Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Clock Generation Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Coded Orthogonal Frequency Division Multiplex (COFDM) Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.4 MPEG Audio Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.5 MPEG-2 Video Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.6 PowerPC 405TM Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.7 Transport Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.8 Video Display System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.0 Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.0 ZL10310/ZL10311 388-pin Package Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 Front End Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3 Video DAC Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 SDRAM Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5 Bit Stream Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.6 Auxiliary External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.7 Peripheral Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.8 Modem/Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.9 Smart Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.10 General Purpose Input Output Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.11 Simplified General Purpose Input Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.12 Inter Integrated Circuit (I2C) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.13 Inter IC Sound (I2S) Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.14 Clock and Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.15 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.16 Reserved Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
IBM(R), the IBM Logo, PowerPC(R) and PowerPC405TM are trademarks of International Business Machines Corporation. Dolby is a trademark of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license or imply a right under any patent, or any other Industrial or Intellectual Property Right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories1. This device is protected by US patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial, home and limited exhibition use only. Reverse engineering or disassembly is prohibited. A valid Macrovision license must be in effect between the purchaser of the ZL10311 IC and Macrovision Corporation. Additional per-chip royalties may be required and are payable by the purchaser to Macrovision.
1. The ZL10311 device is awaiting Dolby Certification
Zarlink Semiconductor Inc.
3
ZL10310/ZL10311
1.0 Device Overview
Data Sheet
Zarlink Semiconductor has designed the ZL10310 and ZL10311 System On a Chip (SoC) devices specifically for DVB-T applications. Integrating a high performance PowerPC 405TM processor with robust industry proven MPEG-2 audio and video decoding, OSD and a COFDM demodulator, the ZL10310 and ZL10311 deliver the performance and functionality required for advanced Digital TV entertainment products. It enables the rapid design and manufacture of cost-effective iDTV and Digital Audio Visual Home Entertainment Centers. The enhanced ZL10311 also supports DVD playback with up to six Dolby Digital1 audio channels. In addition, by integrating the COFDM demodulator, the ZL10310 and ZL10311 enable the implementation of very small footprint TV Adaptor modules.
2.0
Device Interfaces
The following peripheral interfaces are available to the user. Apart from possible level translation and connector buffering, no external devices are required to support any of the interfaces. * * * * * * * * * * * * * * * * 10-bit input that may be configured for an ADC input to the internal COFDM demodulator Additional input bus for additional MPEG-2 Transport Sources AGC (PWM) outputs for a terrestrial tuner Serial control port for a digital tuners Common interface control and bitstream interfaces for an external descrambler Normal PC (PCMCIA) memory module interface for local software updates Unified 64 Mbit SDRAM interface for all decoders and PowerPC 405TM Additional SDRAM interface for high end systems requiring increased memory bandwidth Static memory interface for Flash and external peripherals IDE/ATAPI interface for hard disk and DVD drives External DMA channel and interrupts Six analog video outputs give full flexibility on RGB, S-VHS, and composite signals (with and without OSD) I2S input port from external Digital Stereo source Three I2S ports to external audio DACs for main, surround, and centre channels Dolby surround sound control signals Sony/Philips Digital InterFace (S/PDIF)
If not required in a particular system, any of the peripheral interfaces can be replaced by individual I/O bits from internal general purpose registers. These can then be used for additional purpose, such as interfacing to switches and displays. * * * * * * * Full RS232 interface to an external modem or a 4 wire interface to a Codec IRDA interface or an additional asynchronous serial interface Synchronous serial interface for EEPROM, etc. Two Smart card Interfaces (one instead of a Common Interface) General purpose I2C interface General purpose timer for Infrared (IR) decoding General purpose individual bit I/Os
1. The ZL10311 device is awaiting Dolby Certification
4
Zarlink Semiconductor Inc.
Data Sheet
ZL10310/ZL10311
InfraRed Sensor Analog Video
Comp Video
RGB or Y U/V Tuner Control
A D C
Terrestrial Tuner
ADCIN AGC B
20.48MHz
ZL10310 DTV-SOC
Digital Audio 2 (I S)
D A C
Analog Audio
Serial EEPROM
ADCCLK Common Interface Bitstream o/ps Bitstream i/ps
COFDM Clock Error 20.48MHz Crystal Oscillator
CLK 27IN
Aux Bus
SDRAM1 Bus Aux Bus
SDRAM
External Peripherals
27MHz VCXO
8MB FLASH
Figure 2 - Block diagram of a typical ZL10310-based Free to Air TV Adaptor
3.0
Typical Digital Television (DTV) Receiver
Figure 2 shows a typical Free to Air TV receiver block diagram employing a ZL10310 DTV-SoC device. In its minimal configuration, the ZL10310 DTV-SoC device only requires a single 64 Mbit SDRAM, an audio DAC, and a Flash ROM, which are in addition to a DVB-T tuner front end and a 10-bit analog to digital converter. The Terrestrial Tuner section performs an independent down conversion of the received DVB-T signal from the Antenna, to an IF frequency in the range of 30MHz to 57MHz, dependent on television system (typically 36.17MHz Center Frequency, with 4MHz span). The analogue IF is then converted to the digital domain, with a 10-bit ADC, clocked at 20.48MHz and the resulting Digital output is centered on 15.69MHz. This Digital signal is applied to the ZL10310 via the ADC_IN[9:0] input pins, in the form of a 10-bit parallel signal. The ZL10310 converts the digitized IF from a Terrestrial TV Tuner into an MPEG-2 Transport Stream, which can be optionally de-scrambled (if CA scrambling is used by the broadcaster), and de-multiplexed into separate Packetised Elementary Streams (PES), which are routed to the MPEG Audio and Video decoders, and SI data to the PowerPC 405TM subsystem. Decoded Video can then be mixed and optionally scaled with On-Screen Display (OSD) Graphics generated by the DTV application software. The resultant combination of video and graphics are then routed to the PAL/NTSC Digital ENCoders (DENCs) for display on the TV via the on-chip 10-bit video DACs. Decoded Audio is output directly from the audio decoder sub-system to the I2S and S/PDIF (Sony/Philips Digital InterFace) outputs.
Zarlink Semiconductor Inc.
5
ZL10310/ZL10311
4.0
4.1
Data Sheet
Functional Blocks Overview
Boot ROM
Program execution on the Power PC normally starts from address 0xFFFFFFFC after the internal reset has gone inactive. This would normally be an address in the external Flash ROM (enabled by BI_CS0), but, by forcing the SGPIO2_3 pin low during reset, it is possible to boot from the Internal 8k Boot ROM. The ZL10310 and ZL10311 devices contain an 8k Boot ROM containing code, which is executed under the noted conditions above following a complete system reset (i.e. when main power has been removed from the ZL10310 or ZL10311). The code installed on the Boot ROM, allows the ZL10310/ZL10311 to undertake any of the following 4 functions after a complete reset: 1. Enter ISP (in-system programmable) mode, in which the software in the internal Boot ROM will try booting from an SPI or I2C EEPROM. 2. Try booting from an Atmel Serial Flash device (AT45xxxxx) first, if that fails then enter ISP mode. 3. Try booting from an asynchronous parallel flash device connected to the EBIU bus (CS0) first. If that fails, then try booting from SPI or I2C EEPROM or Serial Flash. 4. Enter debug/monitor mode in which a command prompt is available for debugging registers, downloading code, etc.
4.2
Clock Generation Block
The ZL10310/ZL10311 devices use two separate external clock sources to provide all the clocks required; a 27MHz external Voltage Controlled crystal Oscillator (VCXO), and a 20.48MHz external Crystal Oscillator. A standard 27MHz input to the systems PLL is supplied from an external VCXO. Outputs from this PLL are used to clock the various internal MPEG decoders, the PowerPC micro controller system, and the external SDRAM. The frequency can be adjusted in the ppm range, using a voltage produced by the pulse width modulated frequency error signal, available from GPIO port GP29. The 27MHz input also drives a separate audio PLL that is dedicated to providing 256/512 times the audio sampling rate for the audio decoder and external audio DAC. The COFDM de-modulators have their own PLL driven from an internal 20.48MHz oscillator. An external crystal is required for this oscillator.
6
Zarlink Semiconductor Inc.
Data Sheet
4.3
ZL10310/ZL10311
Coded Orthogonal Frequency Division Multiplex (COFDM) Demodulator
The COFDM demodulator is used to demodulate a digitized COFDM modulated IF signal from the TV Tuner, and ultimately convert the resulting MPEG-2 Transport Stream to the MPEG-2 demultiplexer. The Digitized IF is converted to a complex Baseband signal centered on zero frequency. It also removes adjacent channel interference prior to a Time-to-Frequency Fast Fourier Transform (FFT). The resulting signals are then sent to a digital re-timing block, symbol sync, carrier recovery, and timing recovery. An AGC signal, with a variable mark space ratio, is provided to control the signal levels in the tuner sections of the receiver. Forward Error Correction (FEC) is performed by Viterbi decoding of the convolutional coded data, followed by de-interleaving, Reed-Solomon decoding, and energy dispersal de-randomising. The output is MPEG-2 Transport Stream packets, in byte format. The COFDM demodulator is fully compliant with the ETSI 300 744 and Digital Television Group (DTG) specifications. Key features are: * * * * * * * * * * * * * * FFT processor operates in 2k and 8k carrier mode. 1 All hierarchical and non-hierarchical constellations. Automatic digital carrier recovery over a wide range of offsets without the need for AFC Automatic digital carrier recovery without the need for a VCXO Common phase error correction Channel correction using time and frequency filtering Automatic co - channel protection, frame sync, and fast channel re- acquisition Internal controller handles all tracking and acquisition Viterbi decoding with code rates of 1/2, 2/3, 3/4, 5/6, 6/7, and 7/8 Automatic synchronization and code rate detection Constraint length K = 7 Trace back depth of 128 De-interleaver followed by DVB Reed Solomon error correction De-randomizer and common interface formatting
4.4
MPEG Audio Decoder
The MPEG Audio Decoder produces dual channel outputs from MPEG -1 or MPEG -2 Transport Streams with a maximum rate of 640 kbit/sec. It supports sampling rates of 32, 44.1, and 48 KHz, plus the half rate options. All sampling rates, plus 512/256 Fs, are produced from an internal PLL. A version of the device is available which produces six channels of audio output for holders of the Dolby Digital2 License. * * * * * * * * * Decodes MPEG-1 and dual channel MPEG-2 audio Performs MPEG-1 audio parsing and MPEG-2 Packetised Elementary Stream (PES) audio parsing, or accepts audio elementary streams Supports 32kHz, 44.1 kHz, and 48 kHz sampling rates plus the half rate options All sampling rates, plus 512/256 Fs, derived from an internal PLL 64 step audio attenuation with smooth step transitions SPDIF output meeting IEC1937 specifications Re-locatable ancillary data region Audio Clip Mode Dolby AC3 option2
1. For details on 8k carrier performance and use, please consult Zarlink Field Applications 2. The ZL10311 device is awaiting Dolby Certification
Zarlink Semiconductor Inc.
7
ZL10310/ZL10311
4.5 MPEG-2 Video Decoder
Data Sheet
The MPEG-2 Video Decoder provides complete decoding and synchronized playback of MPEG-2 MP@ML (Main Profile at Main Level) video streams. It supports the decoding of still pictures as well as moving video, with error concealment when necessary. A command driven local controller minimizes the amount of application software needed to control the decoding / channel change process. The decoder accepts PES from the Transport De-multiplexer, with average rates of up to 15 Mbps. PES header parsing supports the extraction of Presentation Time Stamp (PTS) values, which are then used by the audio/ video synchronization hardware. PES or ES streams can be directly decoded from SDRAM in the Video Clip mode of operation. Feature summary: * * * * * * * * Packetised MPEG-2 MP @ ML video streams from the transport demultiplexer or from SDRAM MPEG-1 video (ES) streams from SDRAM Sustained bit rates from 1.5 Mbps to 15 Mbps. Local processor driven by commands from the application processor Sophisticated error concealment based on the use of stored motion vectors from the previous row Supports the decoding of still images Automatic or manual image re-sizing Conversion of MPEG-1, 24 Hz progressive scan, pictures to 60 Hz interlaced (3:2 pull-down)
4.6
PowerPC 405TM Processor
An integrated PowerPC 405TM processor core is provided for applications and control software, and this provides approx. 150 Drhystone MIPS with a clock of 108 MHz. It has instruction and data caches with lock down facilities such that defined areas can be used as general purpose ram. The processor has its own internal bus to which is attached the caches, all the peripherals, and a DMA controller. Code can thus be executed, using internal resources, whilst the MPEG decoders are using the SDRAM. This processor bus is also connected to an auxiliary external bus, which is used for Flash code transfer during the power on routine, and for Flash write operations. PCMCIA, and IDE data transfers also use this bus to provide data and address signals, but their respective control signals have dedicated pins. A bridge to the internal multi-master bus provides software access to the external SDRAM. All internal and external memory is in a unified address space, and a DMA controller supports high speed data transfers. Controllers are provided for two smart cards, an RS232 modem, a serial Codec, an I2C master, a synchronous serial port, and an IRDA interface. Individual bit I/O is also supported. Key Features: * * * * * * * * * PowerPC 405TM Processor Core running at 108 MHz Integrated instruction and data caches (16k/16k) with lock down Integrated set top box peripheral controllers Four channel DMA controller for peripheral and data transfers Dedicated internal processor bus with its own SDRAM controller and auxiliary bus Bridge to the decoder multi-master bus and shared SDRAM Real Time Counters Watch dog timer Interrupt Controller
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Zarlink Semiconductor Inc.
Data Sheet
4.7 Transport Engine
ZL10310/ZL10311
The ZL10310/ZL10311 devices contain a dedicated hardware implementation of an MPEG/DVB transport stream de-multiplexer, with the configuration of this hardware controlled by application software. Included in the hardware are synchronization, Packet Identifier (PID) filtering, clock recovery, de-scrambling, and table section filtering. PID filtered packets are stored in a local buffer, which can hold up to 10 packets before they are moved to the decoders or to memory queues in SDRAM. The queues are used for the tables containing system information. Packets for three destinations can be moved concurrently out of the buffer. The hardware acts in conjunction with a Transport Assist Processor, and the resultant hardware/software combination gives increased adaptability and extended processing capability. Further parsing and filtering is possible, and interrupts can be generated to notify the processor when a given condition has been met. The transport assist processor can then read and manipulate packets whilst they are still in the transport packet buffer. It can then allow data to pass through to SDRAM or the decoders, or can record status information and optionally interrupt the application. Key Features: * * * * * * * * * * * 32 PID values can be used to filter the transport stream Flexible, hardware based, section filtering 64, 4 byte, filter blocks. Filter blocks can be cascaded to provide deep filtering when necessary Hardware Cyclical Redundancy Check (CRC) checking Captured data is transferred to one of thirty two queues in SDRAM Options to transfer complete transport packets with or without headers, or sections Adaptation fields can be delivered to a separate queue Hardware to extract PCR values with option for software filtering to remove long term jitter Comprehensive error detection hardware Integrated DVB descrambler
4.8
Video Display System
The Video Display System provides multi-layered video. This features the On-Screen Display (OSD) for menuing and MHEG-5, the Decoded Video Presentation system, and a Video Blending capability to merge the OSD and Video. The On-Screen Display system is designed to meet or exceed the specifications of major European broadcasters. The final image on the screen is constructed from five separate planes using a fixed display hierarchy. The screen hierarchy consists of: 1. Cursor plane (Top) 2. Region-based graphics plane (typically used for EPG and System menus) 3. Video plane 4. Still image plane (typically used for MHEG-5) 5. Background plane All planes, apart from the background plane, can be separately enabled. The graphics and image planes are region based, and driven by means of bitmaps controlled by a link-list processor. They can operate independently, but have nearly identical operational controls. The size of a bitmap region can vary between 4 pixels wide by 2 pixels deep, and 1K pixels wide and 1K pixels deep. The color resolution of a pixel within a region can be defined by 2, 4, 8, or 16 bits. The 16-bit option is for direct colors; the other options use color look up tables. The Video Presentation system is used to scale and process a decoded Video signal. Decoded Video is stored in Field Stores contained in external SDRAM memory. Prior to display it can be automatically scaled from the original resolution and aspect ratio up to PAL or NTSC full screen size. If the encoded image has a 16:9 aspect ratio, but the display has a 4:3 aspect ratio, then any horizontal scaling factor necessary to fill the screen must be adjusted by
Zarlink Semiconductor Inc.
9
ZL10310/ZL10311
Data Sheet
a further factor of 4/3. Alternatively, a factor of 3/4 can be applied vertically (letter box mode). Video is displayed at the standard PAL or NTSC field rates. Synchronization signals for video presentation can be provided by either the video decoder itself (master mode), or the decoder can slave to incoming signals. The Video Blending System is used to blend the outputs from separate Digital Encoded Video (DENC) blocks for the Video and OSD systems on-chip: 1. RGB - Red Green Blue 2. Y U/V 3. CVBS - Chroma Video Blanking and Sync
5.0
* * * * * *
Physical Specification
The device is contained in a 388-ball Enhanced Plastic Ball-Grid Array (388 EPBGA) package: Body Size: 27mm x 27mm Ball Count: 388 (includes 36 Thermal Balls) Ball Pitch: 1.0mm Ball Matrix: 26 x 26 (partially populated with a 6 x 6 GND matrix in the centre) Ball Diameter 0.60mm Total Package Thickness 2.65mm
Package is viewed from the top side (i.e. through top of the package). Note ball A1 is non-chamfered corner.
Pin A1 Pin A1 ident ident
2 1 A B C D E F G H J K L M N P R T U V W Y 3
4 5
6 7
8 9
10 11
12 13
14 15
16 17
18 19
20 21
22 23
24 25
26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
AA AB AC AD AE AF 1 2 3 4 5 6 7 8 9 11 13 15 17 19 21 23 25 10 12 14 16 18 20 22 24 26
Figure 3 - Package View and Ball Positions
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Zarlink Semiconductor Inc.
Data Sheet 6.0 ZL10310/ZL10311 388-pin Package Pin Descriptions
ZL10310/ZL10311
This section explains the ZL10310 and ZL10311 device pin functions. The following tables are segmented by signal functions. Many of the pins listed below have multiple functions, and in these cases there is information on how the multiplexed function connects to the pin. Many references are made to register settings throughout the Pin Descriptions. The details of the ZL10310 and ZL10311 registers can be found in the Hardware Design Manual for the ZL103xx family of Integrated Digital Television Processors (Publication DM5797), available to customers on request, subject to NDA.
6.1
I
Pin Types
An Input Type with no designator indicates that the signal must be produced by a device using 3.3V outputs, and ESD protection is provided. There is no internal pull up, so unused inputs should be tied high or low. Pin Type indicates that the pin can be programmed with control bits to be used as an input or an output. Pin Type indicates that the pin function can alternate between an input and output depending on the use at that instant i.e. it is Bi-directional. Out characteristics are the same as an Out pin. is an open drain Output.
is a standard 3.3 V, 65 ohm, output, unless otherwise specified. DC drive is 8.2mA/5.4mA @ VH/VL respectively. Maximum slew rate is 75mA/ns, unless otherwise specified.
IO B OD O 5V
is a 5V tolerant Input or Output. An Input Type with a 5V designator indicates that the input tolerates 5V signals. There is no internal pull up.
6.2
Front End Interfaces
Pin No. R02 L02 M03 Function ADCCLK Tuner AGC control Tuner AGC control offset Tuner_SCL Tuner_SDA ED1_MDO[7] (MSB) DV2_IN_DATA[7] (MSB) RW_TDO Pin Type O O 5V O 5V Description Sampling Clock Output to External Tuner IF Analog to Digital Converter. Clock = 20.48MHz. Master AGC Control Output to External TV Tuner Secondary AGC Control Output to External TV Tuner. Used to provide a differential AGC feed to external TV Tuner, if required. External TV Tuner Control Bus - Clock Output External TV Tuner Control Bus - Data Input/Output. External Demodulator 1 Digital Input Data Bit 7 (MSB) Reserved Debug Interface - JTAG TDO (Data Out) 1 1 Notes
Pin Name ADCCLK AGC[0] AGC[1]
GPP[0] GPP[1] EXT_IN[0]
L01 N04 K01
O 5V B 5V I I O
1, 6 1, 6 5, 7 7 3
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ZL10310/ZL10311
Pin Name EXT_IN[1] Pin No. K02 Function ED1_MDO[6] RW_TDI DA_SER_DATAI Pin Type I 5V I 5V I 5V Description
Data Sheet
Notes 1, 5, 7 1, 3 1, 4
External Demodulator 1 Digital Input - Data Bit 6 Debug Interface - JTAG TDI (Data In) Digital Audio Serial Data Input. Main left and right serial audio data at a rate of 64fs. Signal routed through to GP12 (not bonded out) External Demodulator 1 Digital Input - Data Bit 5 Reserved Debug Interface - JTAG Halt External Demodulator 1 Digital Input - Data Bit 4 Reserved Debug Interface - JTAG TMS External Demodulator 1 Digital Input - Data Bit 3 Reserved Debug Interface - JTAG TCK External Demodulator 1 Digital Input - Data Bit 2 Reserved Test Mode A - Test Pin 0 External Demodulator 1 Digital Input - Data Bit 1 Reserved Test Mode A - Test Pin 1 External Demodulator 1 Digital Input - Data Bit 0 (LSB) Reserved Test Mode A - Test Pin 2 External Demodulator 1 Digital Input - Data Valid Input Reserved Test Mode A - Test Pin 3 External Demodulator 1 Digital Input - Clock Input Reserved Test Mode A - Test Pin 4
EXT_IN[2]
J01
ED1_MDO[5] DV2_IN_DATA[6] RW_HALT
I I I I I I I I I I I I I I I I I I I I I I I I
5, 7 7 3 5, 7 7 3 5, 7 7 3 5, 7 7
EXT_IN[3]
L03
ED1_MDO[4] DV2_IN_DATA[5] RW_TMS
EXT_IN[4]
J02
ED1_MDO[3] DV2_IN_DATA[4] RW_TCK
EXT_IN[5]
L04
ED1_MDO[2] DV2_IN_DATA[3] Test[0]
EXT_IN[6]
K03
ED1_MDO[1] DV2_IN_DATA[2] Test[1]
5, 7 7
EXT_IN[7]
H02
ED1_MDO[0] (LSB) DV2_IN_DATA[1] Test[2]
5, 7 7
EXT_IN[8]
G01
ED1_MVAL DV2_IN_DATA[0] (LSB) Test[3]
5 7
EXT_IN[9]
J03
ED1_MCLK DV2_Pixel_Clk Test[4]
5
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Data Sheet
Pin No. V03 Pin Type I I I I I I I I I I I I I I I I I I I I I I I
ZL10310/ZL10311
Function COFDM_ADCIN[8] (MSB) DV2_IN_DATA[7] (MSB) ED2_MDO[7] (MSB) Description COFDM Digital Input from Ext. ADC - Data Bit 8 (MSB) Reserved (when EXT_IN[0] used for JTAG in Debug) External Demodulator 2 Digital Input - Data Bit 7 (MSB) COFDM Digital Input from Ext. ADC - Data Bit 7 External Demodulator 2 Digital Input - Data Bit 6 COFDM Digital Input from Ext. ADC - Data Bit 6 Reserved (when EXT_IN[2] used for JTAG in Debug) External Demodulator 2 Digital Input - Data Bit 5 COFDM Digital Input from Ext. ADC - Data Bit 5 Reserved (when EXT_IN[3] used for JTAG in Debug) External Demodulator 2 Digital Input - Data Bit 4 COFDM Digital Input from Ext. ADC - Data Bit 4 Reserved (when EXT_IN[4] used for JTAG in Debug) External Demodulator 2 Digital Input - Data Bit 3 COFDM Digital Input from Ext. ADC - Data Bit 3 Reserved (when EXT_IN[5] used for JTAG in Debug) External Demodulator 2 Digital Input - Data Bit 2 COFDM Digital Input from Ext. ADC - Data Bit 2 Reserved External Demodulator 2 Digital Input - Data Bit 1 COFDM Digital Input from Ext. ADC - Data Bit 1 Reserved External Demodulator 2 Digital Input - Data Bit 0 (LSB) 2, 5, 7 7 7 2, 5, 7 7 7 2, 5, 7 7 7 2, 5, 7 7 7 2, 5, 7 7 7 2, 5, 7 7 7 Notes 2, 5, 7 7 7 2, 5, 7
Pin Name ADC_IN[0]
ADC_IN[1]
W03
COFDM_ADCIN[7] ED2_MDO[6]
ADC_IN[2]
AA02
COFDM_ADCIN[6] DV2_IN_DATA[6] ED2_MDO[5]
ADC_IN[3]
AB01
COFDM_ADCIN[5] DV2_IN_DATA[5] ED2_MDO[4]
ADC_IN[4]
Y03
COFDM_ADCIN[4] DV2_IN_DATA[4] ED2_MDO[3]
ADC_IN[5]
AB02
COFDM_ADCIN[3] DV2_IN_DATA[3] ED2_MDO[2]
ADC_IN[6]
AC01
COFDM_ADCIN[2] DV2_IN_DATA[2] ED2_MDO[1]
ADC_IN[7]
AA04
COFDM_ADCIN[1] DV2_IN_DATA[1] ED2_MDO[0] (LSB)
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ZL10310/ZL10311
Pin Name ADC_IN[8] Pin No. AA03 Function COFDM_ADCIN[0] (LSB) DV2_IN_DATA[0] (LSB) ED2_MOVAL ADC_IN[9] AC02 DV2_IN_Pixel_Clk ED2_MOCLK
Note Note Note Note Note Note Note 1: 2: 3: 4: 5: 6: 7:
Data Sheet
Pin Type I I I I I
Description COFDM Digital Input from Ext. ADC Data Bit 0 (LSB) Reserved External Demodulator 1 Digital Input Data Valid Input Reserved External Demodulator 1 Digital Input - Clock Input
Notes 2, 5, 7 7
Note 8:
5V tolerant connection to allow use of 5V Tuner devices Multiplex setup with COFDM Register Bit 0 = '1' Multiplex setup with CICSEL3 Register Bits 9:11 = '111' Multiplex setup with CICSEL3 Register Bit 6 = '1', and GPIS2 Register Bits 24:25 = '01' Multiplex setup with COFDM Register Bit 0 = '0' External pull-up to Tuner Vdd PSU required on GPPx lines. The ADC_IN [0:9] and EXT_IN [0:9] inputs on the Front End interface are configured as "Big Endian". This means that bit [0] is the Most Significant Bit (MSB) for the multiplexed functions mapped to that pin. When the ADC_IN [0:9] and EXT_IN [0:9] pins are used to provide various alternative inputs within one application, then each set of inputs must have a tri-state buffer. The enables for these buffers should then be controlled by general purpose I/O pins.
6.3
Video DAC Outputs
Pin Name Pin No. AE15 AD15 AD13 AD10 AF06 AF10 AF11 AF17 AE13 AE14 AE11 AF05 AE09 AF07 Pin Type O O O O O O O O O I O O O I Description Video Triple-DAC 1 output 1. Video Triple-DAC 1 output 2. Video Triple-DAC 1 output 3. Video Triple-DAC 2 output 1. Video Triple-DAC 2 output 2. Video Triple-DAC 2 output 3. De-coupling for triple DAC 1 - to GND De-coupling for triple DAC 1 - to AVDD Gain control for triple DAC 1. Voltage reference input (1.2V) for Video Triple-DAC 1. De-coupling for triple DAC 2 - to GND De-coupling for triple DAC 2 - to AVDD Gain control for triple DAC 2. Voltage reference input (1.2V) for Video Triple-DAC 2 3 4 3 4 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2
DAC_OP0 DAC_OP1 DAC_OP2 DAC_OP3 DAC_OP4 DAC_OP5 DAC1_CREF_OUT DAC1_GREF_OUT DAC1_RREF_OUT DAC1_VREF_IN DAC2_CREF_OUT DAC2_GREF_OUT DAC2_RREF_OUT DAC2_VREF_IN
Note 1:
Video outputs capable of driving between 37.5ohm and 75ohm loads.
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Data Sheet
Note 2: Note 3: Note 4:
ZL10310/ZL10311
Triple DAC output can be setup using the DENCMUX register to output any of the following types of video signal: RGB, CVBS, Y U/V Gain set using Current Adjust resistor to GND. Typically need 392ohms for a DAC load of 37.5ohms. Apply external reference (1.2V) when internal reference is not in use.
6.4
SDRAM Interfaces
The ZL10310 and ZL10311 devices have 2 independent SDRAM interfaces. The main SDRAM interface is SDRAM1 which is used as the main memory space for both the PowerPC processor and Video/Audio decoding. If required a separate processor-only SDRAM interface can be used; this is the optional SDRAM0 interface. All the signals for the SDRAM1 and SDRAM0 interfaces are configured as "Big Endian", which signifies that bit [0] on both the Address and Data buses is the Most Significant Bit (MSB). Pin Type O O O O O O O O O O O O O O B B B B B B B B B
Pin Name SD1_ADDR[00] SD1_ADDR[01] SD1_ADDR[02] SD1_ADDR[03] SD1_ADDR[04] SD1_ADDR[05] SD1_ADDR[06] SD1_ADDR[07] SD1_ADDR[08] SD1_ADDR[09] SD1_ADDR[10] SD1_ADDR[11] SD1_ADDR[12] SD1_ADDR[13] SD1_DATA[00] SD1_DATA[01] SD1_DATA[02] SD1_DATA[03] SD1_DATA[04] SD1_DATA[05] SD1_DATA[06] SD1_DATA[07] SD1_DATA[08]
Pin No. D24 F26 F25 E25 E26 D26 L23 C26 A25 B23 B24 C23 C25 D25 N24 N26 M25 T23 L25 K26 K24 J25 J24
Description SDRAM1 Bus - Address Bit 0 (MSB) SDRAM1 Bus - Address Bit 1 SDRAM1 Bus - Address Bit 2 SDRAM1 Bus - Address Bit 3 SDRAM1 Bus - Address Bit 4 SDRAM1 Bus - Address Bit 5 SDRAM1 Bus - Address Bit 6 SDRAM1 Bus - Address Bit 7 SDRAM1 Bus - Address Bit 8 SDRAM1 Bus - Address Bit 9 SDRAM1 Bus - Address Bit 10 SDRAM1 Bus - Address Bit 11 SDRAM1 Bus - Address Bit 12 SDRAM1 Bus - Address Bit 13 (LSB) SDRAM1 Bus - Data Bit 0 (MSB) SDRAM1 Bus - Data Bit 1 SDRAM1 Bus - Data Bit 2 SDRAM1 Bus - Data Bit 3 SDRAM1 Bus - Data Bit 4 SDRAM1 Bus - Data Bit 5 SDRAM1 Bus - Data Bit 6 SDRAM1 Bus - Data Bit 7 SDRAM1 Bus - Data Bit 8
Notes
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ZL10310/ZL10311
Pin Name SD1_DATA[09] SD1_DATA[10] SD1_DATA[11] SD1_DATA[12] SD1_DATA[13] SD1_DATA[14] SD1_DATA[15] SD1_DQMH SD1_DQML nSD1_RAS nSD1_CAS nSD1_WE SD1_CLK nSD1_CS0 SD0_ADDR[00] SD0_ADDR[01] SD0_ADDR[02] SD0_ADDR[03] SD0_ADDR[04] SD0_ADDR[05] SD0_ADDR[06] SD0_ADDR[07] SD0_ADDR[08] SD0_ADDR[09] SD0_ADDR[10] SD0_ADDR[11] SD0_ADDR[12] SD0_ADDR[13] SD0_DATA[00] Pin No. K25 L26 L24 M26 M24 N25 P25 H25 J26 G25 G24 H24 G26 F24 AC26 AC24 AB25 AB26 AB24 AA24 AA25 Y26 Y25 V24 W24 Y24 AA26 AA23 AE18 Pin Type B B B B B B B O O O O O O O O O O O O O O O O O O O O O B Description SDRAM1 Bus - Data Bit 9 SDRAM1 Bus - Data Bit 10 SDRAM1 Bus - Data Bit 11 SDRAM1 Bus - Data Bit 12 SDRAM1 Bus - Data Bit 13 SDRAM1 Bus - Data Bit 14 SDRAM1 Bus - Data Bit 15 (LSB) SDRAM1 Bus - Data Bus Mask High. Active High SDRAM1 Bus - Data Bus Mask Low. Active High SDRAM1 Bus - Row Address Strobe. Active Low. Also known as SDRAM 1 Command Bit 2 (MSB). SDRAM1 Bus - Column Address Strobe. Active Low. Also known as SDRAM 1 Command Bit 1. SDRAM1 Bus - Write Enable. Active Low. Also known as SDRAM 1 Command Bit 0 (LSB). SDRAM1 Bus - Clock Output SDRAM1 Bus - Chip Select 0. Active Low SDRAM0 Bus. Address bit 0 (MSB) SDRAM0 Bus. Address bit 1 SDRAM0 Bus. Address bit 2 SDRAM0 Bus. Address bit 3 SDRAM0 Bus. Address bit 4 SDRAM0 Bus. Address bit 5 SDRAM0 Bus. Address bit 6 SDRAM0 Bus. Address bit 7 SDRAM0 Bus. Address bit 8 SDRAM0 Bus. Address bit 9 SDRAM0 Bus. Address bit 10 SDRAM0 Bus. Address bit 11 SDRAM0 Bus. Address bit 12 SDRAM0 Bus. Address bit 13 (LSB) SDRAM0 Bus - Data Bit 0 (MSB)
Data Sheet
Notes
1
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Data Sheet
Pin Type B B B B B B B B B B B B B B B O O O O O O O
ZL10310/ZL10311
Pin No. AD19 AD20 AF20 AD21 AE21 AE22 AF23 AD23 AD22 AF22 AF21 AC21 AE20 AE19 AF18 AE24 AD18 AD25 AF24 AE23 AE26 AD26 Description SDRAM0 Bus - Data Bit 1 SDRAM0 Bus - Data Bit 2 SDRAM0 Bus - Data Bit 3 SDRAM0 Bus - Data Bit 4 SDRAM0 Bus - Data Bit 5 SDRAM0 Bus - Data Bit 6 SDRAM0 Bus - Data Bit 7 SDRAM0 Bus - Data Bit 8 SDRAM0 Bus - Data Bit 9 SDRAM0 Bus - Data Bit 10 SDRAM0 Bus - Data Bit 11 SDRAM0 Bus - Data Bit 12 SDRAM0 Bus - Data Bit 13 SDRAM0 Bus - Data Bit 14 SDRAM0 Bus - Data Bit 15 (LSB) SDRAM0 Bus - Data Bus Mask High. Active High SDRAM0 Bus - Data Bus Mask Low. Active High SDRAM0 Bus - Row Address Strobe. Active Low. Also known as SDRAM0 Command Bit 2 (MSB). SDRAM0 Bus - Column Address Strobe. Active Low. Also known as SDRAM0 Command Bit 1. SDRAM0 Bus - Write Enable. Active Low. Also known as SDRAM0 Command Bit 0 (LSB). SDRAM0 Bus - Clock Output SDRAM0 Bus - Chip Select 0. Active Low 1 Notes
Pin Name SD0_DATA[01] SD0_DATA[02] SD0_DATA[03] SD0_DATA[04] SD0_DATA[05] SD0_DATA[06] SD0_DATA[07] SD0_DATA[08] SD0_DATA[09] SD0_DATA[10] SD0_DATA[11] SD0_DATA[12] SD0_DATA[13] SD0_DATA[14] SD0_DATA[15] SD0_DQMH SD0_DQML nSD0_RAS nSD0_CAS nSD0_WE SD0_CLK nSD0_CS0
Note 1:
SD0_CLK / SD1_CLK output is 50ohm impedance with 130ma/ns slew rate
6.5
Bit Stream Interfaces
The ZL10310 and ZL10311 devices have a fully DVB-compatible byte-wide Common Interface, which is a bitstream data Input/Output bus. There are multiplexed functions on these pins, and included is information on how to access these multiplexed signals. The multiplexed functions include access to Address/Data Bits of the Auxiliary External Bus (configured on this interface to access PCMCIA (PC) Cards), RISC Trace debug ports, Simplified GPIO Bus 1 and Smart Card Interface 1. The Data pins for Output (MOD[0:7]) and Input (MID[0:7]) are configured as "Big Endian". This means that bit [0] is the Most Significant Bit (MSB) for the Common Interface and Auxiliary Bus signals.
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ZL10310/ZL10311
Data Sheet
The provision of options, and the avoidance of the need for external pull ups, precludes the use of 5 volt tolerant inputs. The use of a 5-volt smart card would thus require external level translators. Pin Name MOD[0] Pin No. T02 Pin Type O O
Function CIO_MOD[0] (MSB) RESET_4
Description Common Interface Output - Data Bit 0 [MSB] Bit 4 output from RESET Register. Also mapped to PCMCIA interface Address Bit 25. Common Interface Output - Data Bit 1 Bit 3 output from RESET Register. (PCMCIA Address 24) Common Interface Output - Data Bit 2 Auxiliary External Bus - Address Bit 8 (PCMCIA Address 23) RISC Trace Port Clock Output Common Interface Output - Data Bit 3 Auxiliary External Bus - Address Bit 9 (PCMCIA Address 22) RISC Trace Port 6 (Debug) / RISC Trace Data Bit 7 (Debug) Common Interface Output - Data Bit 4 Auxiliary External Bus - Address Bit 10 (PCMCIA Address 21) RISC Trace Port 5 (Debug) / RISC Trace Data Bit 6 (Debug) Common Interface Output - Data Bit 5 Auxiliary External Bus - Address Bit 11 (PCMCIA Address 20) RISC Trace Port 4 (Debug) / RISC Trace Data Bit 5 (Debug) Common Interface Output - Data Bit 6 Simplified General Purpose Input / Output Bus 1 - Bit 4 Smart Card 1 Interface - Vcc Enable Output Auxiliary External Bus - Address Bit 12 (PCMCIA Address 19) RISC Trace Port 3 (Debug) / RISC Trace Data Bit 4 (Debug)
Notes 1 2
MOD[1]
R01
CIO_MOD[1] RESET_3
O O O O O O O O O O O O O O O IO O O O
1 2 1 2 3 1 2 3 1 2 3 1 2 3 1 4 5 2 3
MOD[2]
P03
CIO_MOD[2] BI_ADDR_8 RT_CLK
MOD[3]
P02
CIO_MOD[3] BI_ADDR_9 RT_TS6 / RT_DATA[7]
MOD[4]
P01
CIO_MOD[4] BI_ADDR_10 RT_TS5 / RT_DATA[6]
MOD[5]
N02
CIO_MOD[5] BI_ADDR_11 RT_TS4 / RT_DATA[5]
MOD[6]
M01
CIO_MOD[6] SGPIO1_4 SC1_VCC_CMND BI_ADDR_12 RT_TS3 / RT_DATA[4]
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Data Sheet
Pin Name MOD[7] Pin No. M02 Pin Type O IO B O O O
ZL10310/ZL10311
Function CIO_MOD[7] SGPIO1_0 SC1_IO BI_ADDR_13 RT_TS20 / RT_DATA[3] Description Common Interface Output - Data Bit 7 (LSB) Simplified General Purpose Input / Output Bus 1 - Bit 0 Smart Card 1 Interface - Data I/O Auxiliary External Bus - Address Bit 13 (PCMCIA Address 18) RISC Trace Port 20 (Debug) / RISC Trace Data Bit 3 (Debug) Common Interface Output - Data Valid Indicator. Data Valid for the Current Clock Cycle for Transmission. Simplified General Purpose Input / Output Bus 1 - Bit 2 Smart Card 1 Interface - Detect Input Auxiliary External Bus - Address Bit 15 (PCMCIA Address 16) RISC Trace Port 10 (Debug) / RISC Trace Data Bit 2 (Debug) Common Interface Output - Packet Start Indicator. Identifies the first byte in a transport packet of 188 bytes. Simplified General Purpose Input / Output Bus 1 - Bit 3 Smart Card 1 Interface - Reset Output Auxiliary External Bus - Address Bit 14 (PCMCIA Address 17) RISC Trace Port 2E (Debug) / RISC Trace Data Bit 1 (Debug) Common Interface Output - Bitstream Clock. Simplified General Purpose Input / Output Bus 1 - Bit 1 Smart Card 1 Interface - Clock Output Auxiliary External Bus - Address Bit 16 (PCMCIA Address 15) RISC Trace Port 1E (Debug) / RISC Trace Data Bit 0 (Debug) Notes 1 4 5 2 3 1
MOVAL
T01
CIO_MVAL
SGPIO1_2 SC1_DETECT BI_ADDR_15 RT_TS10 / RT_DATA[2] MOSTRT R03 CIO_MSTRT
IO I O O O
4 5 2 3 1
SGPIO1_3 SC1_RESET BI_ADDR_14 RT_TS2E / RT_DATA[1] MOCLK N03 CIO_MCLK SGPIO1_1 SC1_CLK BI_ADDR_16 RT_TS1E / RT_DATA[0]
IO O O O O IO O O O
4 5 2 3 1 4 5 2 3
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ZL10310/ZL10311
Pin Name MID[0] Pin No. Y02 Function CII_MDATA[0] (MSB) BI_DATA[0] (MSB) MID[1] Y01 CII_MDATA[1] BI_DATA[1] MID[2] T04 CII_MDATA[2] BI_DATA[2] MID[3] U03 CII_MDATA[3] BI_DATA[3] MID[4] V01 CII_MDATA[4] BI_DATA[4] MID[5] V02 CII_MDATA[5] BI_DATA[5] MID[6] U01 CII_MDATA[6] BI_DATA[6] MID[7] T03 CII_MDATA[7] (LSB) BI_DATA[7] (LSB) MISTRT U02 CII_MSTRT Pin Type I I I I I I I I I I I I I I I I I Description Common Interface Input - Bit 0 (MSB) Auxiliary External Bus - Data Bit 0 (MSB) (PCMCIA Data 15) Common Interface Input - Bit 1 Auxiliary External Bus - Data Bit 1 (PCMCIA Data 14) Common Interface Input - Bit 2 Auxiliary External Bus - Data Bit 2 (PCMCIA Data 13) Common Interface Input - Bit 3 Auxiliary External Bus - Data Bit 3 (PCMCIA Data 12) Common Interface Input - Bit 4 Auxiliary External Bus - Data Bit 4 (PCMCIA Data 11) Common Interface Input - Bit 5 Auxiliary External Bus - Data Bit 5 (PCMCIA Data 10) Common Interface Input - Bit 6 Auxiliary External Bus - Data Bit 6 (PCMCIA Data 9) Common Interface Input - Bit 7 (LSB) Auxiliary External Bus - Data Bit 7 (LSB) (PCMCIA Data 8)
Data Sheet
Notes 1, 6 2, 6 1, 6 2, 6 1, 6 2, 6 1, 6 2, 6 1, 6 2, 6 1, 6 2, 6 1, 6 2, 6 1, 6 2, 6
Common Interface Input - Packet Start Indicator. Identifies the first byte in a transport packet of 188 bytes. Common Interface Input - Bitstream Clock. Common Interface Input - Data Valid Indicator. Data Valid for the Current Clock Cycle for Transmission.
MICLK MIVAL
W02 AA01
CII_MCLK CII_MVAL
I I
Note Note Note Note Note Note
1: 2: 3: 4: 5: 6:
Multiplex setup with PORTMUX Register Bits [11:10] = `00' Multiplex setup with PORTMUX Register Bits [11:10] = `10' Multiplex setup with PORTMUX Register Bits [11:10] = `11' Multiplex setup with PORTMUX Register Bits [11:10] = '01' & CICSEL3 Register Bit 2 = '0'. Also if BI_DATA[7] = '0' at Reset. Multiplex setup with PORTMUX Register Bits [11:10] = '01' & CICSEL3 Register Bit 2 = '1'. Also if BI_DATA[7] = '1' at Reset. Data Inputs MID [0:7] should be connected to GND or Vdd if NOT required.
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Data Sheet
6.6 Auxiliary External Bus
ZL10310/ZL10311
The ZL1031 and ZL10311 devices have an Auxiliary External Bus, which can be configured as an IDE interface to external Hard-Disk Drives and other ATAPI devices. The Auxiliary Bus can also offer a standard interface to external memory chips, such as Flash ROM etc. There are multiplexed functions on these pins, and included is information on how to access these multiplexed signals. The multiplexed functions include access to the DVB Common Interface Address Bus. The Data and Address pins for the Auxiliary External Bus are configured as "Big Endian". This means that Data bit [0] and Address Bit [9] are the Most Significant Bits (MSB). Pin No. A05 Pin Type O O O O O O O O O O O O O O O O O O O O O O O
Pin Name BI_ADDR[09]
Function BI_ADDR[09] (MSB) nBI_CS5
Description Auxiliary External Bus - Address Bit 9 (MSB) Auxiliary External Bus - Chip Select 5. Active Low. Auxiliary External Bus - Address Bit 10 Auxiliary External Bus - Address Bit 11 Auxiliary External Bus - Address Bit 12 Auxiliary External Bus - Address Bit 13 Auxiliary External Bus - Address Bit 14 IDE IO write signal. Active Low. DVB Common Interface IO write signal Auxiliary External Bus - Address Bit 15 IDE IO read signal. Active Low. DVB Common Interface IO read signal Auxiliary External Bus - Address Bit 16 Auxiliary External Bus - Address Bit 17 DVB Common Interface Address Bit 14 (MSB) Auxiliary External Bus - Address Bit 18 DVB Common Interface Address Bit 13 Auxiliary External Bus - Address Bit 19 DVB Common Interface Address Bit 12 Auxiliary External Bus - Address Bit 20 DVB Common Interface - Address Bit 11 Auxiliary External Bus - Address Bit 21 DVB Common Interface - Address Bit 10
Notes 1 2
BI_ADDR[10] BI_ADDR[11] BI_ADDR[12] BI_ADDR[13] BI_ADDR[14]
A13 A15 C14 D14 B16
BI_ADDR[10] BI_ADDR[11] BI_ADDR[12] BI_ADDR[13] BI_ADDR[14] nIDE_iowr nDVB_CI_iowr
3 4 5 3 4 5
BI_ADDR[15]
A17
BI_ADDR[15] nIDE_iord nDVB_CI_iord
BI_ADDR[16] BI_ADDR[17]
B17 A18
BI_ADDR[16] BI_ADDR[17] DVB_CI_A[14] (MSB)
6 5 6 5 6 5 6 5 6 5
BI_ADDR[18]
C16
BI_ADDR[18] DVB_CI_A[13]
BI_ADDR[19]
B18
BI_ADDR[19] DVB_CI_A[12]
BI_ADDR[20]
D16
BI_ADDR[20] DVB_CI_A[11]
BI_ADDR[21]
C17
BI_ADDR[21] DVB_CI_A[10]
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ZL10310/ZL10311
Pin Name BI_ADDR[22] Pin No. B19 Function BI_ADDR[22] DVB_CI_A[9] BI_ADDR[23] A21 BI_ADDR[23] DVB_CI_A[8] BI_ADDR[24] C19 BI_ADDR[24] DVB_CI_A[7] BI_ADDR[25] C20 BI_ADDR[25] DVB_CI_A[6] BI_ADDR[26] B21 BI_ADDR[26] DVB_CI_A[5] BI_ADDR[27] C21 BI_ADDR[27] DVB_CI_A[4] BI_ADDR[28] B22 BI_ADDR[28] DVB_CI_A[3] BI_ADDR[29] A23 BI_ADDR[29] DVB_CI_A[2] BI_ADDR[30] C22 BI_ADDR[30] DVB_CI_A[1] BI_ADDR[31] A24 BI_ADDR[31] (LSB) / BI_WBE1 DVB_CI_A[0] (LSB) BI_DATA[00] BI_DATA[01] BI_DATA[02] BI_DATA[03] BI_DATA[04] BI_DATA[05] BI_DATA[06] BI_DATA[07] BI_DATA[08] G02 F01 H03 G03 F02 E01 F03 E02 D01 BI_DATA[00] (MSB) BI_DATA[01] BI_DATA[02] BI_DATA[03] BI_DATA[04] BI_DATA[05] BI_DATA[06] BI_DATA[07] BI_DATA[08] Pin Type O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Description Auxiliary External Bus - Address Bit 22 DVB Common Interface - Address Bit 9 Auxiliary External Bus - Address Bit 23 DVB Common Interface - Address Bit 8 Auxiliary External Bus - Address Bit 24 DVB Common Interface - Address Bit 7 Auxiliary External Bus - Address Bit 25 DVB Common Interface - Address Bit 6 Auxiliary External Bus - Address Bit 26 DVB Common Interface - Address Bit 5 Auxiliary External Bus - Address Bit 27 DVB Common Interface - Address Bit 4 Auxiliary External Bus - Address Bit 28 DVB Common Interface - Address Bit 3 Auxiliary External Bus - Address Bit 29 DVB Common Interface - Address Bit 2 Auxiliary External Bus - Address Bit 30 DVB Common Interface - Address Bit 1 Auxiliary External Bus - Address Bit 31 (LSB) / Write Byte Enable Bit 1
Data Sheet
Notes 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5
DVB Common Interface Address Bit 0 (LSB) Auxiliary External Bus - Data Bit 0 (MSB) Auxiliary External Bus - Data Bit 1 Auxiliary External Bus - Data Bit 2 Auxiliary External Bus - Data Bit 3 Auxiliary External Bus - Data Bit 4 Auxiliary External Bus - Data Bit 5 Auxiliary External Bus - Data Bit 6 Auxiliary External Bus - Data Bit 7 Auxiliary External Bus - Data Bit 8
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Zarlink Semiconductor Inc.
Data Sheet
Pin No. F04 E03 D02 C01 B01 C02 D03 B13 Pin Type O O O O O O O O
ZL10310/ZL10311
Function BI_DATA[09] BI_DATA[10] BI_DATA[11] BI_DATA[12] BI_DATA[13] BI_DATA[14] BI_DATA[15] (LSB) nBI_CS0 Description Auxiliary External Bus - Data Bit 9 Auxiliary External Bus - Data Bit 10 Auxiliary External Bus - Data Bit 11 Auxiliary External Bus - Data Bit 12 Auxiliary External Bus - Data Bit 13 Auxiliary External Bus - Data Bit 14 Auxiliary External Bus - Data Bit 15 (LSB) Auxiliary External Bus - Chip Select 0. Active Low. Disabled if Internal Boot ROM enabled. Used for Flash ROM. Auxiliary External Bus - Chip Select 1. Active Low. DVB Common Interface - Card Enable. Active Low. Auxiliary External Bus - Chip Select 2. Active Low. IDE Bus Chip select 0. Active Low. O O O Auxiliary External Bus - Chip Select 3. Active Low. IDE Bus Chip select 1. Active Low. Auxiliary External Bus - Output Enable for ALL Aux. bus devices (including Common Interface). Active Low. DVB Common Interface - Output Enable. Active Low. Auxiliary External Bus - Data Ready Input. Optional transfer complete signal from an external device. DVB Common Interface - Wait. Auxiliary External Bus Read/NOT Write Output. Auxiliary External Bus - Write Byte Enable 0. Active Low. DVB Common Interface Write-enable Output. 6 5 6 5 8 9 8 9 6 Notes
Pin Name BI_DATA[09] BI_DATA[10] BI_DATA[11] BI_DATA[12] BI_DATA[13] BI_DATA[14] BI_DATA[15] nBI_CS0
nBI_CS1
C13
nBI_CS1 nDVB_CI_Card _Enable
O O O
nBI_CS2
A12
nBI_CS2 nIDE_CS0
nBI_CS3
B11
nBI_CS3 nIDE_CS1
nBI_OE
C11
nBI_OE
DVB_CI_oe
O
5
BI_READY
C04
BI_READY
I 5V
6
DVB_CI_wait BI_RnW nBI_WBE0 B07 B12 BI_RnW nBI_WBE0 DVB_CI_we
O 5V O O O
5
Zarlink Semiconductor Inc.
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ZL10310/ZL10311
Pin Name nEDMAC3_ACK Pin No. B06 Function nEDMAC3_ACK nIDE_DMA_ACK nEDMAC3_REQ A06 nEDMAC3_REQ nIDE_DMA_REQ nIDE_OE INT2 AD16 E24 nIDE_OE INT2 Pin Type O O I I O I Description
Data Sheet
Notes
External DMA Port 3 Acknowledge Output for an IDE controller. Active Low. IDE Acknowledge Output. Active Low. External DMA Port 3 Request Input from an IDE Controller. Active Low. IDE DMA Request Input. Active High. IDE Output Enable signal for a bus transceiver in the IDE data path. Active Low. PowerPC External Interrupt #2 Input. Connect to VDD_IO or ground if not required.
Note Note Note Note Note Note
1: 2: 3: 4: 5: 6:
Multiplex Multiplex Multiplex Multiplex Multiplex Multiplex
setup setup setup setup setup setup
with with with with with with
PORTMUX Register Bit [7] = `0' PORTMUX Register Bit [7] = `1' CIC Control Register Bit 3 = '1', & Bit 30 or Bit 31 = '0' CIC Control Register Bit 3 = '1', & Bit 30 or Bit 31 = '1' CIC Control Register Bit 3 = '0' CIC Control Register Bit 3 = '1'
6.7
Peripheral Port
The Peripheral Port is provided with 10 pins that can be configured as general purpose I/O bits, or can provide several alternative interfaces. The bit I/Os are provided by the GPIS (input) and GPOS (output) registers, along with the PORTMUX and CIC Control Register bits, and only the bits listed below should be used. There are multiplexed functions on these pins, and included is information on how to access these multiplexed signals. The multiplexed functions include access to GPIO signals, DMA control signals, Infrared Port, Serial Communications port, S/PDIF Audio bitstream output and some ancillary Common Interface Video control signals. Pin Name PP[0] Pin No. C12 Pin Type IO I O IO
Function GPIO_22 INT9 EDMAC2_ACK EBM_HOLDACK
Description General Purpose Input/Output - Bit 22 PowerPC External Interrupt #9 Input DMA Channel 2 External Acknowledge Output External Bus Master (master/slave bus arbitration controls) Hold Acknowledge flag
Multiplex Configuration PORTMUX Reg. Bit 8 = '0', GPOS Reg Bits 44:45 = '00' PORTMUX Reg Bit 8 = '0', GPIS3 Reg Bits 44:45 = '01' PORTMUX Reg Bit 8 = '1', CIC Control Reg bits 26:27 = '10' PORTMUX Reg Bit 8 = '1', CIC Control Reg bits 26:27 = '11'
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Zarlink Semiconductor Inc.
Data Sheet
Pin Name PP[1] Pin No. F23 Pin Type IO O I IO
ZL10310/ZL10311
Function GPIO_04 nSD1_CS1 nEDMAC2_REQ EBM_HOLDREQ Description General Purpose Input/Output - Bit 4 SDRAM1 Bus Chip Select 1. Active Low DMA Channel 2 External Request Input. Active Low. External Bus Master (master/slave bus arbitration controls) - Hold Request flag General Purpose Input/Output - Bit 24 Serial Port 1 / iRDA port Receive data General Purpose Input/Output - Bit 25 Serial Port 1 / iRDA port Transmit data General Purpose Input/Output - Bit 8 Serial Communications Port - Baud-rate Clock output System Clock output (54MHz) General Purpose Input/Output - Bit 7 Serial Communications Port - Receive Data Input DMA Channel 2 External End Of Transfer External Bus Master - Bus Request flag (master/slave bus arbitration controls) Multiplex Configuration PORTMUX Reg Bit 8 = '0', GPOS Reg bits 8:9 = '00' PORTMUX Reg Bit 8 = '0', GPOS Reg bits 8:9 = '10' PORTMUX Reg Bit 8 = '1', CIC Control Reg bits 26:27 = '10' PORTMUX Reg Bit 8 = '1', CIC Control Reg bits 26:27 = '11' PORTMUX Reg Bit 3 = '0' PORTMUX Reg Bit 3 = '1' PORTMUX Reg Bit 3 = '0' PORTMUX Reg Bit 3 = '1' PORTMUX Reg Bit 13 = '0', GPOS Reg Bits 16:17 = '00' PORTMUX Reg Bit 13 = '0', GPOS & GPIS1 Reg Bits 16:17 = '01' PORTMUX Reg Bit 13 = '1' PORTMUX Reg Bit 2 = '0', GPOS Reg Bits 14:15 = '00' PORTMUX Reg Bit 2 = '0', GPIS1 Reg Bits 14:15 = '01' PORTMUX Reg Bit 2 = '1', CIC Control Reg bits 26:27 = '10' PORTMUX Reg Bit 2 = '1', CIC Control Reg bits 26:27 = '11'
PP[2]
AE05
GPIO_24 SERIAL1/ INFRARED_RXD
IO I IO O IO O
PP[3]
AC16
GPIO_25 SERIAL1/ INFRARED_TXD
PP[4]
AD17
GPIO_08 SCP_CLK
SYSCLK PP[5] AD09 GPIO_07 SCP_RXD EDMAC2_EOT EBM_BUSREQ
O IO I IO IO
Zarlink Semiconductor Inc.
25
ZL10310/ZL10311
Pin Name PP[6] Pin No. AF02 Function GPIO_06 SCP_TXD CI_PACKET_ START INT3 PP[7] AE10 GPIO_18 DV_ TRANSPARENCY _ GATE SERIAL1 /INFRARED_CLK SERIAL1 /INFRARED _nCTS PP[8] C09 GPIO_21 INT8 DA_IEC958 PP[9] AC25 GPIO_05 nSD0_CS1 DV1_PIXEL_ CLOCK
Note 1:
Data Sheet
Pin Type IO O I
Description General Purpose Input/Output - Bit 6 Serial Communications Port - Transmit Data Output DVB Common Interface Transport Packet Start indicator. PowerPC External Interrupt #3 Input General Purpose Input/Output - Bit 18 Reserved
Multiplex Configuration PORTMUX Reg Bit 2 = '0', GPOS Reg Bits 12:13 = '00' PORTMUX Reg Bit 2 = '0', GPOS Reg Bits 12:13 = '01' PORTMUX Reg Bit 2 = '0', GPIS2 Reg Bits 12:13 = '01' PORTMUX Reg Bit 2 = '1' PORTMUX Reg Bit 4 = '0', GPOS Reg Bits 36:37 = '00' PORTMUX Reg Bit 4 = '0', GPOS & GPIS1 Reg Bits 36:37 = '01' PORTMUX Reg Bit 4 = '0', GPIS3 Reg Bits 36:37 = '01' PORTMUX Reg Bit 4 = '1'. Over-ruled when PORTMUX Reg bits 6:5 = '10' to select the SERIAL1 CTS input on MCP[1]. PORTMUX Reg Bit 0 = '0', GPOS Reg Bit 42:43 = '00' PORTMUX Reg Bit 0 = '0', GPIS3 Reg Bit 42:43 = '01' PORTMUX Reg Bit 0 = '1' PORTMUX Reg Bit 1 = '0', GPOS Reg bits 10:11 = '00' PORTMUX Reg Bit 1 = '0', GPOS Reg bits 10:11 = '10' PORTMUX Reg Bit 1 = '1'
B IO IO
I I
Serial Port 1 / iRDA port Clock Input Serial Port 1 / iRDA port Clear-To-Send Input. Active Low. General Purpose Input/Output - Bit 21 PowerPC External Interrupt #8 Input Digital Audio S/PDIF (IEC 958) Serial Data Output General Purpose Input/Output - Bit 5 SDRAM0 Bus Chip Select 1. Active Low Reserved
IO I O IO O O
DV_ TRANSPARENCY_ GATE Output controlled by the OSD bitmap; used to control the drivers of another pixel bus. Programmable polarity.
6.8
Modem/Codec Interface
This interface allows a full 16550-compatible UART interface, a standard serial Port for iRDA, and a Synchronous RS232-compatible Modem interface. There is also provision for 4 GPIO ports. When MCP7:4 provide a 4-wire Codec interface, MCP3:0 would normally be used to provide four more general purpose I/O bits but can alternatively supply additional Serial 1 flags. When a full RS232 Modem interface is required, the complete MCP interface must be used for Serial 0 signals.
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Zarlink Semiconductor Inc.
Data Sheet
ZL10310/ZL10311
The software options provided allow a full interface to an external Modem, using the Serial 0 interface, whilst still leaving a basic Serial 1 interface on the Peripheral Port (see section 6 above, in the Pin Descriptions section). Pin Name MCP[0] Pin No. T24 Pin Type I O IO I I IO O O IO I I IO O O I 5V I 5V I 5V I 5V O 5V IO 5V
Function SERIAL0/16550_RI SERIAL1/INFRARED_ RTS GPIO_28
Description Serial Port 0 / 16550 UART Ring Indicator Input Serial Port 1 / iRDA port Request-To-Send Output General Purpose Input/Output - Bit 28 Serial Port 0 / 16550 UART Data Carrier Detect Input Serial Port 1 / iRDA port Clear-To-Send Input. Active Low. General Purpose Input/Output - Bit 27 Serial Port 0 / 16550 UART Data Terminal Ready Output Serial Port 1 / iRDA port Data Terminal Ready Output General Purpose Input/Output - Bit 26 Serial Port 0 / 16550 UART Data Set Ready Input Serial Port 1 / iRDA port Data Set Ready Input General Purpose Input/Output - Bit 23 Serial Port 0 / 16550 UART Transmit Data Output Synchronous Serial Port for Modem Transmit Data Output Serial Port 0 / 16550 UART Receive Data Input Synchronous Serial Port for Modem Received Data Input Serial Port 0 / 16550 UART Clear-To-Send Input. Active Low. Synchronous Serial Port for Modem Baud Rate Clock Serial Port 0 / 16550 UART Request-To-Send Output. Synchronous Serial Port for Modem Frame Sync
Notes 1 2 3 1 2 3 1 2 3 1 2 3 4 5 4 5 4 5 4 5
MCP[1]
V25
SERIAL0/16550_DCD nSERIAL1/INFRARED_ CTS GPIO_27
MCP[2]
P23
SERIAL0/16550_DTR SERIAL1/INFRARED_ DTR GPIO_26
MCP[3]
U26
SERIAL0/16550_DSR SERIAL1/INFRARED_ DSR GPIO_23
MCP[4]
T26
SERIAL0/16550_TXD SSP_TXD
MCP[5]
U25
SERIAL0/16550_RXD SSP_RXD
MCP[6]
V26
nSERIAL0/16550_CTS SSP_CLK
MCP[7]
P24
nSERIAL0/16550_RTS SSP_FS
Note 1:
Multiplex setup with PORTMUX Register Bits [6:5] = `11'
Zarlink Semiconductor Inc.
27
ZL10310/ZL10311
Note Note Note Note 2: 3: 4: 5: Multiplex Multiplex Multiplex Multiplex setup setup setup setup with with with with PORTMUX Register Bits [6:5] = `10' PORTMUX Register Bits [6:5] = `0x' CIC Control Register Bit 2 = `0' and Bit 28 = `1' CIC Control Register Bits 2 = `1', Bit 28 = '1' and CICSEL3 Register Bit 6 = '0'
Data Sheet
6.9
Smart Card Interface
Pin No. AD05 Function SGPIO0_0 SC0_IO Pin Type IO 5V B 5V IO 5V O 5V IO 5V I 5V IO 5V O 5V IO 5V O 5V Description Simplified General Purpose Input / Output Bus 0 - Bit 0 Smart Card 0 Interface - Data I/O Simplified General Purpose Input / Output Bus 0 - Bit 1 Smart Card 0 Interface - Clock Output Simplified General Purpose Input / Output Bus 0 - Bit 2 Smart Card 0 Interface - Detect Input Simplified General Purpose Input / Output Bus 0 - Bit 3 Smart Card 0 Interface - Reset Output Simplified General Purpose Input / Output Bus 0 - Bit 4 Smart Card 0 Interface - Vcc Enable Output Notes 1 2 1 2 1 2 1 2 1 2
Pin Name SGPIO0[0]
SGPIO0[1]
AC03
SGPIO0_1 SC0_CLK
SGPIO0[2]
AF04
SGPIO0_2 SC0_DETECT
SGPIO0[3]
AD06
SGPIO0_3 SC0_RESET
SGPIO0[4]
AF03
SGPIO0_4 SC0_VCC_COMMAND
Note 1: Note 2:
Multiplex setup with CICSEL3 Register Bit 1 = '0'. Also if BI_DATA[6] = '0' at Reset. Multiplex setup with CICSEL3 Register Bit 1 = '1'. Also if BI_DATA[6] = '1' at Reset.
6.10
General Purpose Input Output Interfaces
The General Purpose Input Output Interface is provided with 10 pins that can be configured as general purpose I/O bits, or can provide several alternative interfaces. The bit I/Os are provided by the GPIS (input) and GPOS (output) registers, and only the bits listed below should be used. Care should be observed when programming the registers allocated to each of the GPIO ports. There are multiplexed functions on these pins, and included is information on how to access these multiplexed signals. The multiplexed functions include access to GPIO signals, I2C bus, I2S Audio Output signals, Test interface signals, Clock signals, Video Sync Signals, Synchronous Serial Port signals and a VCXO error signal.
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Zarlink Semiconductor Inc.
Data Sheet
Pin Name GP00 Pin No. AF16 Pin Type IO B O
ZL10310/ZL10311
Function GPIO_00 I2C1_SCL DA_DEEMPHASIS0 Description General Purpose Input/Output - Bit 0 I2C (Inter Integrated Circuit) Bus 1 Serial Clock IO Digital Audio De-emphasis indicator bit 0 Output. (See Note 1). Digital Audio Dolby Surround Mode bit 0. (See Note 2) Device Test Mode A Enable. (See Note 4) General Purpose Input/Output - Bit 1 I2C (Inter Integrated Circuit) Bus 1 Serial Data IO Digital Audio De-emphasis indicator bit 1 Output. (See Note 1). Digital Audio Dolby Surround Mode bit 1. (See Note 2) Debug-Mode Enable. (See Note 4) General Purpose Input/Output - Bit 2 Digital Composite Video Sync Output Auxiliary External Bus Chip Select 4. Active Low. Digital Audio Dolby Surround Mode bit 0. (See Note 2) PowerPC External Interrupt #4 Input Multiplex Configuration GPOS Reg Bits 0:1 = '00' GPOS Reg Bits 0:1 ='01' GPIS1 Reg Bits 0:1 = '01' GPOS Reg Bits 0:1 = '10'
DA_SURMOD0 TEST_MODE_A GP01 AD04 GPIO_01 I2C1_SDA DA_DEEMPHASIS1
O I IO B O
GPOS Reg Bits 0:1 = '11' GPOS Reg Bits 2:3 = '00' GPOS Reg Bits 2:3 ='01' GPIS1 Reg Bits 2:3 = '01' GPOS Reg Bits 2:3 = '10'
DA_SURMOD1 DEBUG_MODE GP02 AC06 GPIO_02 AV_CSYNC nBI_CS4 DA_SURMOD0 INT4
O I IO 5V I 5V O 5V O 5V I 5V
GPOS Reg Bits 2:3 = '11' GPOS Reg Bits 4:5 = '00' GPIS1 Reg Bits 4:5 = '01' GPOS Reg Bits 4:5 = '01' GPOS Reg Bits 4:5 = '11' GPIS Reg Bits 4:5 = `11'
Zarlink Semiconductor Inc.
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ZL10310/ZL10311
Pin Name GP03 Pin No. AF12 Function GPIO_03 SYS_CLK nBI_CS5 INT5 DA_SURMOD1 PM15 Pin Type IO O O I O I Description General Purpose Input/Output - Bit 2 System Clock output (54MHz) Auxiliary External Bus Chip Select 5. Active Low. PowerPC External Interrupt #5 Input Digital Audio Dolby Surround Mode bit 1. (See Note 2) Boot-Option Input - map to PORTMUX Register Bit 15. (See Note 5). General Purpose Input/Output - Bit 10 General Purpose Timer Capture Timer 1 Input. Typically an Interrupt from an Infrared receiver. Auxiliary External Bus - Chip Select 7. Active Low. General Purpose Input/Output - Bit 16 Digital Audio Serial Data. Surround channel serial audio data at a rate of 64fs. (Dolby-enabled devices only) Auxiliary External Bus Chip Select 4. Active Low. General Purpose Input/Output - Bit 17 Digital Audio Serial Data. Centre channel/Subwoofer serial audio data at a rate of 64fs. (Dolby-enabled devices only) Auxiliary External Bus Chip Select 5. Active Low. Boot-Option Input - map to PORTMUX Register Bit 14. (See Note 5).
Data Sheet
Multiplex Configuration GPOS Reg Bits 6:7 = '00' GPOS Reg Bits 6:7 = '01' GPOS Reg Bits 6:7 = '10' GPIS3 Reg Bits 6:7 = '01' GPOS Reg Bits 6:7 = '11' -
GP10
AD07
GPIO_10 GPT_CAPT1
IO I
GPOS Reg Bits 20:21 = '00' GPIS3 Reg Bits 20:21 = '01'
nBI_CS7 GP16 A04 GPIO_16 DA_SERIAL_DATA1
O IO O
GPOS Reg Bits 20:21 = '11' GPOS Reg Bits 32:33 = '00' GPOS Reg Bits 32:33 = '01'
nBI_CS4 GP17 C07 GPIO_17 DA_SERIAL_DATA2
O IO O
GPOS Reg Bits 32:33 = '10' GPOS Reg Bits 34:35 = '00' GPOS Reg Bits 34:35 = '01'
nBI_CS5 PM14
O I
GPOS Reg Bits 34:35 = '10' -
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Zarlink Semiconductor Inc.
Data Sheet
Pin Name GP19 Pin No. D21 Pin Type IO 5V I 5V IO 5V I 5V I 5V
ZL10310/ZL10311
Function GPIO_19 GPT_CAPT0 DV2_VSYNC SSP_FS DA_LR_CH_CLK Description General Purpose Input/Output - Bit 19 General Purpose Timer Capture Timer 0 Input Reserved Synchronous Serial Port for Modem - Frame Sync I2S Digital Audio Left-Right Channel Indicator Input. (see Note 3) General Purpose Input/Output - Bit 20 PowerPC External Interrupt #5 Input Reserved Synchronous Serial Port for Modem - Baud rate clock I2S Digital Audio 64fs clock input. Signal routed through to GP13 (not bonded out) General Purpose Input/Output - Bit 29 System VCXO Pulse-Width modulated Error Signal. (See Note 6) Multiplex Configuration GPOS Reg Bits 38:39 = '00' GPIS1 Reg Bits 38:39 = '01' GPOS Reg Bits 38:39 = '10', GPIS2 Reg Bits 38:39 = '01' GPIS2 Reg Bits 28:29 = '01' CICSEL3 Reg Bit 6 = '1', GPIS2 Reg Bits 28:29 = '01' GPOS Reg Bits 40:41 = '00' GPIS1 Reg Bits 40:41 = '01' GPOS Reg Bits 40:41 = '10', GPIS2 Reg Bits 40:41 = '01' GPIS3 Reg Bits 40:41 = '01' CICSEL3 Reg Bit 6 = '1', GPIS2 Reg Bits 26:27 = '01' GPOS Reg Bits 58:59 = '00' GPOS Reg Bits 58:59 = '10'
GP20
AC11
GPIO_20 INT23 DV2_HSYNC SSP_CLK DA_BIT_CLK
IO 5V I 5V IO 5V I 5V I 5V
GP29
AE04
GPIO_29 XPT_PWM_OUTPUT
IO 5V O 5V
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
DA_DEEMPHASIS [1:0] have following truth-table: `00' = No emphasis, `01' = 50-15 ms emphasis, `10' = Reserved, `11' = CCITT J.17 DA_SURMOD[1:0] used to indicate whether Dolby Digital encoded stream has been encoded in Dolby Surround. DA_LR_CH_CLK (via GP19) is a clock whose phase indicates the presence of left hand or right hand data, and whose rate is equivalent to fs. Signal routed through to GP14 (not bonded out). GP00 and GP01 inputs are Latched during Power-up only. Active Low Input at power-up to enable Boot Mode functions. GP03 and GP17 inputs are Latched at Power-up only. GP29 XPT_PWM_OUTPUT Compensates for frequency errors in 27MHz external VCXO.
6.11
Simplified General Purpose Input Output Interface
The Simplified General Purpose Input Output Interface is provided with 8 pins that can be configured as general purpose I/O bits. As there is only one mapped SGPIO signal mapped to each of the pins, the interface is simple, with SGPIO inputs monitored using the SGPI input register, and outputs set using the SGPO register. The Reserved signals are configured as "Big Endian". This means that DV1_DATA [0] is the Most Significant Bit (MSB).
Zarlink Semiconductor Inc.
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ZL10310/ZL10311
Pin No. A11 Pin Type IO B IO B IO B IO B I
Data Sheet
Pin Name SGPIO2[0]
Function SGPIO2_0 DV1_DATA[0] (MSB)
Description Simplified General Purpose Input / Output Bus 2 - Bit 0 Reserved Simplified General Purpose Input / Output Bus 2 - Bit 1 Reserved Simplified General Purpose Input / Output Bus 2 - Bit 2 Reserved Simplified General Purpose Input / Output Bus 2 - Bit 3 Reserved Boot Mode. Latched during Power-up only. Pull low with resistor to boot from internal ROM. Leave floating to boot via external memory via BI_CS0. Simplified General Purpose Input / Output Bus 2 - Bit 4 Reserved Simplified General Purpose Input / Output Bus 2 - Bit 5 Reserved Simplified General Purpose Input / Output Bus 2 - Bit 6 Reserved Simplified General Purpose Input / Output Bus 2 - Bit 7 Reserved
Notes 1 2, 3 1 2, 3 1 2, 3 1 2, 3
SGPIO2[1]
B10
SGPIO2_1 DV1_DATA[1]
SGPIO2[2]
B08
SGPIO2_2 DV1_DATA[2]
SGPIO2[3]
B09
SGPIO2_3 DV1_DATA[3] BOOT_MODE
SGPIO2[4]
C10
SGPIO2_4 DV1_DATA[4]
IO B IO B IO B IO B
1 2, 3, 4 1 2, 3, 4 1 2, 3, 4 1 2, 3, 4
SGPIO2[5]
A09
SGPIO2_5 DV1_DATA[5]
SGPIO2[6]
A07
SGPIO2_6 DV1_DATA[6]
SGPIO2[7]
C08
SGPIO2_7 DV1_DATA[7] (LSB)
Note Note Note Note
1: 2: 3: 4:
Multiplex setup with CICSEL3 Register Bit 3 = '0' Multiplex setup with CICSEL3 Register Bit 3 = '1' Latched input. Must NOT be pulled Low during chip reset. CICVCR Register Bit 23 = `1' sets DV1_DATA to an Output, `0' sets to an input
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Zarlink Semiconductor Inc.
Data Sheet
6.12 Inter Integrated Circuit (I2C) Interface
ZL10310/ZL10311
The I2C interface provides a highly programmable interface to the industry-standard I2C (inter-integrated circuit) serial bus. The I2C device contains a selection of functions that can be programmed to operate as a master, as a slave, or as both a master and a slave on the I2C interface. I2C, unlike other designs, requires a minimum amount of software to manage the I2C bus. In addition to sophisticated I2C bus protocol management, the I2C device provides full data buffering, eliminating any time-dependent program interaction and further simplifying the task of connecting to the I2C bus. The I2C interface complies with the Philips(R) Semiconductors I2C Specification, dated 1995. Both the SCL and SDA pins require an external pull-up to 3.3V; minimum resistor value of 1067 ohms. Pin Name I2C0_SCL I2C0_SDA Pin No. R25 R26 Pin Type O O Description I2C Bus Clock. Dedicated open drain clock. I2C Bus Data. Dedicated open drain serial data/address.
6.13
Inter IC Sound (I2S) Audio Interface
The PCM Audio Output Controller provides an I2S Audio Interface. The audio outputs can be internally muted, and a separate control output is not required. S/PDIF, surround, and center serial outputs can be obtained by using Peripheral or General Purpose Port pins. Pin No. C06 B04 Pin Type O O
Pin Name DA_BIT_CLK DA_LR_CH_CLK
Description Digital Audio 64fs clock Output Digital Audio Left-Right Channel Indicator Output. A clock whose phase indicates the presence of left hand or right hand data, and whose rate is equivalent to fs. Digital Audio Oversampling Clock Output. 512/256 fs clock Digital Audio Serial Data Output. Main left and right serial audio data at a rate of 64fs
DA_OSAMP_CLK DA_SER_DATA0
A03 D06
O O
6.14
Clock and Reset Interface
The Clock and Reset interface provides inputs for the 2 primary clock signals, and also a System Reset input. Pin Name OSC_PAD OSC_PADN CLK27_IN NG_SYS_RST Pin No. C05 B03 C18 A20 I I Pin Type Description COFDM Crystal Oscillator - 20.48MHz Crystal Connection positive. Also External 20.48MHz CXO Input COFDM Crystal Oscillator - 20.48MHz Crystal Connection negative. Main System Clock Input - 27MHz from External VCXO Power-On Reset Input, from external POR generator. Active Low. Must be held low for at least 100 microseconds after the 1.8V supply has been established. Connect to GND in normal operation. Defines production Test Mode B
TMODE
B05
I
Zarlink Semiconductor Inc.
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ZL10310/ZL10311
6.15 Power Supply Pins
Data Sheet
The ZL10310 and ZL10311 devices operate from 3 voltages; 3.3V for the Input/Outputs, 2.5V for the Video DACs and 1.8V for the SoC Core. The table below shows the pins to which each of the supply voltages should be connected. Pin Name GND Pin No.s A1, A2, A8, A14, A19, A26, B2, B25, B26, C3, C24, D4, D9, D13, D18, D23, H1, H26, J4, J23, N1, N23, P4, P26, V4, V23, W1, W26, AC4, AC9, AC14, AC18, AC23, AD3, AD24, AE1, AE2, AE25, AF1, AF8, AF13, AF19, AF25, AF26 D10, D12, D15, D17, K4, K23, M4, M23, R4, R23, U4, U23, AC10, AC12, AC15, AC17 AC5, AC7, AC8, AC19, AC20, AC22, E23, G23, H23, W23, Y23, AB23, D5, D7, D8, D19, D20, D22, E4, G4, H4, W4, Y4, AB4 B14 C15 B15 A16 A22 B20 A10 D11 AE12, AD14, AE16 AC13, AF14, AF15, AE17 AF09, AE08, AE07 Digital Ground (used in parallel with Thermal_GND pins) Description Nominal Voltage Supply 0V
VDD_Core
VDD Supplies to ZL10310/ZL10311 Core
+1.8V wrt GND
VDD_IO
VDD Supplies to ZL10310/ZL10311 I/O pins
+3.3V wrt GND
AUD_GNDA0 AUD_GNDA1 AUD_VDDA0 AUD_VDDA1 CLK_GNDA CLK_VDDA COFDM_GNDA COFDM_VDDA DAC1_AGND DAC1_AVDD DAC2_AGND
Analog GND for Audio PLL 1 Analog GND for Audio PLL 2 Analog VDD for Audio PLL 1 Analog VDD for Audio PLL 2 Analog GND for System Clock PLL (27MHz) Analog VDD for System Clock PLL (27MHz) Analog GND for COFDM PLL (20.48MHz) Analog VDD for COFDM PLL (20.48MHz) Analog GND for Video Triple-DAC 1 Analog VDD for Video Triple-DAC 1 Analog GND for Video Triple-DAC 2
0V 0V +1.8V wrt AUD_GND +1.8V wrt AUD_GND 0V +3.3V wrt CLK_GND 0V +1.8V wrt COFDM_GND 0V +2.5V wrt DAC1_AGND 0V
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Zarlink Semiconductor Inc.
Data Sheet
ZL10310/ZL10311
Pin No.s AD12, AD11, AE06, AD08 L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16, R11, R12, R13, R14, R15, R16, T11, T12, T13, T14, T15, T16 Description Analog VDD for Video Triple-DAC 2 Thermal Ground pins (used in parallel with Digital GND pins (GND)) Nominal Voltage Supply +2.5V wrt DAC2_AGND 0V
Pin Name DAC2_AVDD Thermal_GND
6.16
Reserved Connections
The following pins have no specific function allocated, and are reserved. Pin No. W25 U24 R24 T25 AE03 AD01 AD02 AB03 Pin Type Analog IO Analog IO Analog IO Analog IO O 5V O 5V O 5V B 5V Connection NOT CONNECTED NOT CONNECTED NOT CONNECTED NOT CONNECTED NOT CONNECTED NOT CONNECTED NOT CONNECTED NOT CONNECTED
Zarlink Semiconductor Inc.
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ZL10310/ZL10311
7.0
7.1
Data Sheet
Characteristics
AC and DC Electrical Characteristics
Absolute Maximum Ratings
Parameter Supply voltage wrt GND, 1.8 V supply Supply voltage wrt GND, 2.5V supply Supply voltage wrt GND, 3.3 V supply Storage temperature Bias for 5V inputs Input Voltage (any input pin) Output Voltage (any output pin) ESD Rating (Static Discharge) Max Junction Temperature
Min
Max +2.3 +3.0 +3.9
Units V V V C V V V V C
-65 (GND-0.5) (GND-0.5)
150 +5.5 (Vdd_IO+0.5) (Vdd_IO+0.5) 3k 110
DC Characteristics Symbol TA Parameter Operating Free Air Temperature Thermal Resistance, Junction to Case Digital Core Supply Voltage Digital IO Supply Voltage Audio Clock PLL Supply Voltage System Clock PLL Supply Voltage COFDM Oscillator Supply Voltage Video Triple-DAC 1 Supply Voltage Video Triple-DAC 2 Supply Voltage Supply Current, 1.8 V Supply Current, 2.5 V 1.71 3.14 1.71 3.14 1.71 2.38 2.38 Min 0 18 1.80 3.30 1.80 3.30 1.80 2.50 2.50 550 80 1.89 3.47 1.89 3.47 1.89 2.62 2.62 750 100 Typ Max 70 Unit C C/Watt V V V V V V V mA mA VDD_CORE = Max DACx_AVDD = Max Conditions
jc
VDD_CORE VDD_IO AUD_VDDA0, 1 CLK_VDDA COFDM_VDDA DAC1_AVDD DAC2_AVDD IDD_CORE IDD_DACS
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Zarlink Semiconductor Inc.
Data Sheet
DC Characteristics Symbol IDD_IO PD CLK27_IN_Freq COFDM_OSC_ Freq COFDM_OSC_Tol Parameter Supply Current, 3.3 V Power Dissipation System Input Clock Frequency COFDM Input Clock Frequency COFDM Crystal Oscillator Tolerance Min Typ 40 1.78 27 20.48 50 Max 75 2.0 Unit mA W MHz MHz ppm
ZL10310/ZL10311
Conditions VDD_IO = Max ALL VDD pins = Max External VCXO External Crystal Oscillator
Zarlink Semiconductor Inc.
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ZL10310/ZL10311
Data Sheet
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Zarlink Semiconductor Inc.
1 2
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1
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I
c Zarlink Semiconductor 2002 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1 213807 25Nov02
For more information about all Zarlink products visit our Web Site at
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Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
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